AMD Zen 7 Specifications Leaked: Up to 288 Cores, Flagship to Launch in Late 2028
According to the latest revelations from Moore'sLawIsDead, AMD's next-generation server platform Zen 7 EPYC flagship (codename Florence) will feature up to 8 Steamboat CCDs with 36 cores each, reaching 288 cores per processor. Florence will utilize two Dwarka I/O chips and two Mathura memory chips, all based on TSMC N3C process.
Each Steamboat CCD consists of a Zen 7 core chip manufactured on TSMC A14 node, stacked with an L3 cache chip on N4P node. Unlike existing 3D V-Cache, the cache chip is stacked below the core chip, not above.
Each core is equipped with 7MB of L3 cache, supports PCIe 6.0 and CXL 3.2 interfaces, xGMI4-80G interconnect speed, and a maximum TDP of 600W.
On the timeline, the A0 tape-out is planned for October 2026, with mass production targeted for mid-2028, and the official release expected in late 2028.
In addition, a PCIe Gen 7 platform has also appeared on the roadmap, expected to arrive in 2029, potentially as a mid-generation update for the new interface.
For users, a key piece of information is compatibility. Leaked documents show that Zen 7 CCDs are compatible with previous generation Kedar and Weisshorn I/O chips, while Silverton CCDs support Badri, Kedar, Puri, and Dwarka IOD, covering SP7 and SP8 packaging, and supporting 2/4/6/8 CCDs per socket.
Leaked performance data for Silverton and Silverking targeting the consumer market shows a 16%-20% performance increase per core in server workloads below 9W; and an energy efficiency improvement of 30%-36% in client APU scenarios at 3W/core.
MLID speculates that the size of the 36-core Steamboat CCD is similar to the 16-core Silverton. Theoretically, AMD could fit two Steamboats into the AM5 package, resulting in a 72-core desktop processor.
However, the leaked slides do not confirm such a product, and MLID himself believes that these chips are more likely to be aimed at the embedded market rather than DIY enthusiasts.