JEDEC Announces LPDDR6 Advancement Roadmap: Up to 512GB per Chip, Surpassing DDR5
JEDEC has officially released the next-generation roadmap for LPDDR6 low-power memory. Most notably, LPDDR6 memory chips are expected to reach a capacity of 512GB per chip, significantly exceeding the current mainstream server DDR5. Current mainstream server DDR5 typically has a capacity of 64GB-128GB per module, with an even larger gap in single-die capacity.
The reason LPDDR6 can achieve such a dramatic capacity breakthrough lies in JEDEC's addition of a narrower x6 subchannel mode, allowing a single package to accommodate more memory dies.
Combined with more advanced manufacturing processes that increase the density of each die, the final result is a single chip capable of carrying the capacity previously achievable by an entire memory module.
This means that future AI servers will be able to easily build TB-level memory pools, significantly reducing the painful "moving" of data between memory and solid-state drives, and in turn doubling the execution efficiency of model inference.
In addition to capacity, LPDDR6's traditional advantages are becoming more pronounced. The base 16Gb LPDDR6 already operates at speeds exceeding 10.7Gbps, a 33% increase in processing speed compared to the previous generation, with core power consumption reduced by more than 20% simultaneously.
At the same time, the SOCAMM2 compact module standard based on LPDDR6 is being developed in parallel to replace the traditional, thick DDR5 modules, providing AI servers with a higher-integration, low-power memory base.
For ordinary gaming and creative users, the advancement of LPDDR6 will not happen overnight, but within the next three years, high-end gaming laptops, tablets, or AIPC are expected to obtain ultra-large memory.
More importantly, while maintaining lightness, thinness, and battery life, running large models with hundreds of billions of parameters or large-scale simulation rendering on the edge will become the norm.