JEDEC Accelerates DDR6 Standard Advancement, Expected to Enter Commercial Stage in 2028
The next-generation DDR6 memory standard for desktop and server platforms is approaching, with storage chip manufacturers collaborating with JEDEC to develop related specifications. According to Korean media TheElec, major storage manufacturers such as SK Hynix, Samsung, and Micron have initiated DDR6 design in their labs and are gradually coordinating module development plans with substrate manufacturers. This collaborative R&D is led by JEDEC, an industry standards organization, to ensure a unified technical foundation for the new generation of memory at the design level.
It is reported that as early as 2024, relevant manufacturers could access the first draft of the DDR6 standard from JEDEC, but key parameters such as voltage range, signal definition, power consumption packaging, and pin layout have not yet been finalized. With the recent increase in industry promotion efforts, these gaps are expected to be gradually filled, and the standard finalization process will accelerate accordingly. Several leading manufacturers have actually moved beyond the sample stage and entered a more rigorous verification cycle to pave the way for subsequent mass production.
Regarding the performance indicators that have attracted external attention, currently disclosed information shows that the initial target transfer rate for DDR6 is 8,800 MT/s, with plans to expand upwards to 17,600 MT/s, almost doubling the current speed limit of DDR5. The core of this significant speed increase lies in DDR6's adoption of a 4x24-bit subchannel architecture, which requires introducing new design approaches in terms of signal integrity. In contrast, current DDR5 still uses a 2x32-bit subchannel structure. The difference in channel partitioning between the two generations of standards will pose new requirements for controller design, wiring, and PCB layers.
Against the backdrop of traditional DIMM modules encountering physical limitations at high frequencies, the industry generally places its hopes on CAMM2 technology to alleviate the multiple bottlenecks of high-speed signals in space, routing, and interface forms. Current indications suggest that server platforms are likely to be the first to adopt DDR6, followed by gradual expansion to high-end laptop platforms after capacity ramp-up. Desktop consumer products may follow slightly later.
Looking at the timeline, the industry previously reported that DDR6 would be "launched" in 2027, but the latest assessment is more inclined to view 2027 as a key customer verification stage, with large-scale commercialization facing the market expected to be achieved in 2028. At the same time, with the shipment of new-generation servers and the overall application penetration rate of DDR5 reaching approximately 80% last year, and expected to further climb to around 90% this year, the role of DDR4 in the industrial chain is gradually being seen as a "phase-out" generation. This not only reserves more sufficient market space for new standards but also helps release foundry capacity for the large-scale production of subsequent DDR6 chips and modules.